module bps(clk,rst,bps_clk);
input clk,rst;
output bps_clk;
reg bps_clk;
reg [15:0] m;
 
 ///////分频进程, 50Mhz 的时钟 326 分频  9600的16倍频/////////
always @(posedge clk)
begin
	if(!rst)
	begin
		bps_clk<=0;  m<=4'd0;
	end
	else
	begin
	
	if(m==16'd163)
	begin
		bps_clk<=~bps_clk;
		m<=m+1;
	end
	else if(m==16'd326)
	begin
		bps_clk<=~bps_clk;
		m<=16'd0;
	end
	else begin
		m<=m+16'd1;
	end
end
end
endmodule
